The TTPController is an integrated CMOS device which implements the functionalities and features of the SAE AS6003 standard established back in 2011. It is designed using our DO 254-compliant C2NF chip IP and is commercially available in its third generation. Its datasheet is available in the Downloads section below.
Application fields
Standard TTP® controllers are commercially available from TTTech since 1999. Although the open TTP standard was not developed for a specific application field, it clearly targets safety-critical applications due to built-in redundancy and fault-tolerance mechanisms as well as the development guidelines followed. Main use is in aviation (see press release) for modular/distributed real-time control systems. See our case studies for Honeywell MAC and the Boeing 787 Dreamliner. The TTP controller is also used in fly-by-wire systems on the Embraer 190-E2, Embraer Legacy and Praetor, and the Airbus A220.
Certified off-the-shelf communication controller
The TTP chip IP and supporting embedded software were designed to meet the stringent requirements of RTCA DO-254 / EUROCAE ED-80 and DO-178B up to the highest Design Assurance Level (DAL A) and got certified in a long list of projects. TTTech supports new projects with certification data packages and highly experienced engineers.
Downloads
Key benefits
- Dual-channel controller for redundant data transfers
- Dedicated controller supporting TTP (time-triggered protocol class C)
- Suited for dependable distributed real-time systems with guaranteed response time
- Asynchronous data rate up to 5 Mbit/s (MFM/Manchester)
- Synchronous data rate 5 to 25 Mbit/s
- Bus interface (speed, encoding) for each channel selectable independently
- 40 MHz main clock with support for 10 MHz crystal, 10 MHz oscillator or 40 MHz oscillator
- 16 MHz bus guardian clock with support for 16 MHz crystal or 16 MHz oscillator
- Single power supply 3.3V, 0.35 µm CMOS process
- 80 pin LQFP80 Package
- Operating temperature range from -40ºC to 125ºC
- 16k x 16 SRAM for message, status, control area (communication network interface) and for scheduling information (MEDL)
- 4k x 16 (plus parity) instruction code RAM for protocol execution code
- Data sheet conforms to protocol revision 2.04
- 16k x 16 instruction code ROM containing startup execution code and deprecated protocol code revision 1.00
- 16 Bit non-multiplexed asynchronous host CPU interface
- 16 Bit RISC architecture
- Software tools, design support, development boards available
- Certification support package according to RTCA/DO-254 DAL A available
- RoHS compliant
Application notes
Application notes are available on request and in our Customer Service area (limited to customers)