TTEEnd System Chip IP Core Space

This chip IP core for modern FPGAs (field programmable gate-arrays) or as building block for the design of ASICs is available as synthesized netlist or bitstream.

The highly optimized end system IP enables the design-in of real-time Ethernet communication capabilities between an embedded computer and TTEthernet switches in demanding, safety-critical space applications.

Key Benefits

  • For fully deterministic data communication networks
  • Compliant to Time-triggered Ethernet SAE AS6802
  • Fault-tolerant clock synchronization
  • Supporting IEEE 802.3 full-duplex switched Ethernet and ARINC 664 part 7 compliant data traffic
  • 2/3 x 10/100/1000 Mbps Ethernet ports
  • ARINC 653 compliant sampling and queuing ports for critical traffic
  • Redundancy management for critical traffic
  • Smallest end system IP core offered so far