Small satellites are widely recognized as growth field in the space market providing efficient means for low-cost access to space and in-orbit demonstration of new technologies. However, typical challenges to endure are the limited funds for development and testing of the space vehicle and the related software (software clearly being a key element of steadily rising complexity) as well as the very strong size, weight and power constraints. The SAFESAT project proposes valuable research into the application of several already existing concepts in order to address these challenges.
The extremely low size, weight and power required for nanosatellites, combined with increasing performance and functional complexity challenges can only be addressed with a computing architecture with a very small number of highly integrated and high performance hardware components. Virtualization and partitioning are key mechanisms for achieving such simplification of the hardware architecture, whilst maintaining strong safety and reliability guarantees. Various hypervisors make it possible to virtualize hardware access, while TTEthernet provides partitioning at the network level. With the correct operating system support, a safe separation between partitions enables a mixed-criticality environment where software errors in one part of the system can never interfere operation in other parts.
In line with ESA’s SAVOIR architecture and the DLR’s OBC-SA approach, a modular platform including virtualization, safe time and space partitioning will be created. This will allow small satellite developers to effectively use and re-use the latest high-performance FPGAs (SoCs) – initially for experimentation (non-critical payloads) and on the medium term also for their avionics.
Cost savings are achieved by having flexible, reconfigurable hardware platforms that can be used both on the ground (in the development phase) and in space (in the deployment phase). Ideally the platform is small and light-weight and its power consumption can be optimized (balanced). These objectives can be met by applying state-of-the-art concepts for larger spacecraft also to nanosatellites including CubeSats.
The SAFESAT project partners TTTech Computertechnik AG and TU Graz bring know-how in safe and reliable data networking, partitioning and system architecture together with know-how in developing, building and operating nanosatellites.
Within the SAFESAT project, TTTech will develop the mixed-criticality platform for safe operation based on a system-on-chip solution and implement its TTEthernet real-time mixed-criticality communication technology on the platform. In particular, the focus will be on the adaptation towards the space environment based on the requirements of small satellite platforms. The project adds value to the technology-related development for space applications and will lead the way towards space-graded products manufactured in Austria. The experimental proof of concept allows to transfer concepts out of previous research to a different target platform and further developing its TTEthernet IP for future European space missions, raising its TRL from TRL3 to TRL4, while adding an in-flight validation opportunity since elements of the test bed could be re-used in the ESA OPS-SAT nanosatellite which is planned to launch in 2016.