FIT - Fault Injection into the Time-triggered architecture
The objective of the EC-funded research project FIT was to validate the system concepts of TTP-based architectures. A number of different hardware and software based fault-injection methods were applied to determine the error-detection coverage of time-triggered architecture in a realistic application.
(Project duration 2000-2002)
SETTA - Systems Engineering for Time-Triggered Architectures
Focus of the SETTA project was the systems engineering of time-triggered architectures. SETTA was concerned with reducing development time and increasing safety by simulation. TTTech developed a schedule verification tool to detect design and implementation errors at an early stage of the development cycle.
(Project duration 2000-2002)
TTA - Time-Triggered Architecture
The EU-funded project TTA was aimed at the implementation of a time-triggered computer architecture for fault-tolerant distributed real-time systems and its deployment in safety-critical transportation systems. Its key component was a communication controller executing TTP. The chip's protocol firmware was developed by TTTech.
(Project duration 1996-1998)
X-By-Wire
X-By-Wire, officially named "Safety-related Fault-tolerant Systems in Vehicles", was an EU-funded Brite-Euram research project. Mission of this project was to create a framework for the introduction of safety-related fault-tolerant electronic systems without mechanical backup in vehicles. Additionally the preconditions for mass production of by-wire systems were evaluated.
(Project duration 1996-1998)
